Active termination control through module register

ABSTRACT

A method and apparatus are provided for active termination control in a memory by an module register providing an active termination control signal to the memory. The module register monitors a system command bus for read and write commands. In response to detecting a read or write command, the module register generates an active termination control signal to the memory. The memory turns on active termination based on information programmed into one or more mode registers of the memory. The memory maintains the active termination in an on state for a predetermined time based on information programmed into one or more mode registers of the memory.

RELATED APPLICATIONS

The present application is a divisional of U.S. application Ser. No.10/383,939, filed Mar. 7, 2003; which claims priority to U.S.Provisional Application No. 60/427,917, filed Nov. 20, 2002; each ofwhich is incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to memory devices. In particular itrelates to active termination control following read and write commandsin memory devices.

BACKGROUND OF THE INVENTION

Many electronic systems employ controllers and memory devices that sendinformation back and forth among each other. Typically, the informationis transmitted on one or more system buses. These buses act astransmission lines. Consequently, these buses require designs thatconsider signal reflections associated with devices coupled to atransmission line. Typically, transmission lines are terminated using aresistor coupled between the transmission line and a power supply node.

For electronic systems, such as computers, termination is provided byexternal resistors that are often located on the motherboard of thecomputer. An external resistor having an impedance that matches theimpedance of the transmission line is selected to terminate atransmission line such as the interconnection signal lines of busesconnecting a plurality of integrate circuits. When the externalresistance matches the resistive component of the transmission lineimpedance, there is little or no signal reflection. However, externalresistors for all the signal lines located on system boards use a largeamount of area on these boards.

As an alternative to external resistors, on chip termination or on dietermination, also known as active termination, can be used on theintegrated circuits of the system. Using on chip termination requiresadditional interconnection between the devices of the system such as thecontrollers and the memories. This additional interconnection alsorequires that the controllers and other devices of the system useadditional pin connectors. The amount of additional connection lines andpin connections on the various devices depends on the overall design forproviding on chip termination.

What is needed is a means of providing control of active terminationcontrol that is flexible and does not require the addition of a largernumber of pin connections for an electronic system.

SUMMARY OF THE INVENTION

A solution to the problems as discussed above is addressed in thepresent invention. A method and apparatus are provided for activetermination control in a memory by an module register providing anactive termination control signal to the memory. The module registermonitors a system command bus for read and write commands. In responseto detecting a read or write command, the module register generates anactive termination control signal to the memory. The memory turns onactive termination based on information programmed into one or more moderegisters of the memory. In one embodiment, the memory column addressstrobe (CAS) latency is used to determine a turn on time, and the memoryburst length (BL) is used to determine a turn off time following theturn on of the active termination. The turn on time is set at the CASlatency minus a number of clock cycles. After the active termination isturned on, it is maintained on for a length of time set equal to about anumber of cycles equal to BL/2 for a Double Data Random Access Memory(referred to as DDR) plus one and one-half clock cycles. For a memorythat reads and writes one data bit per cycle, the active termination ismaintained on for a length of time set equal to about the number ofcycles equal to the BL of the memory.

These and other embodiments, aspects, advantages, and features of thepresent invention will be set forth in the description that follows, andin part will become apparent to those skilled in the art by reference tothe following description of the invention and referenced drawings or bypractice of the invention. The aspects, advantages, and features of theinvention are realized and attained by means of the instrumentalities,procedures, and combinations particularly pointed out in the appendedclaims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an embodiment of a information handling system including acomputer system having a controller coupled to memory modules, inaccordance with the teachings of the present invention.

FIG. 2 shows an embodiment of a system having a controller coupled tomemory modules, in accordance with the teachings of the presentinvention.

FIG. 3 shows an embodiment of a module register having a decodingcircuit, a plurality of input command ports, chip select ports, andactive termination port for outputting an active termination controlsignal, in accordance with the teachings of the present invention.

FIG. 4 shows an embodiment of a decoding circuit of a module registerhaving an active termination control port for outputting an activetermination control signal based on signals received on chip selectports and a plurality of input command ports, in accordance with theteachings of the present invention.

FIG. 5 shows an embodiment of a memory including a control logic coupledto an active termination control port for receiving an activetermination control signal and coupled to an active termination, inaccordance with the teachings of the present invention.

FIG. 6 shows an embodiment of an extended mode register having bitlocations, which provide information for active termination control, inaccordance with the teachings of the present invention.

FIG. 7 shows an embodiment of a mode register using bit locations, whichprovide information for active termination control, in accordance withthe teachings of the present invention.

FIG. 8 shows a flow diagram of an embodiment for a method for activetermination control, in accordance with the teachings of the presentinvention.

FIG. 9 shows a flow diagram of another embodiment for a method foractive termination control, in accordance with the teachings of thepresent invention.

FIG. 10 shows a flow diagram of another embodiment for a method forextending active termination control, in accordance with the teachingsof the present invention.

FIG. 11 shows a timing diagram for a write operation to memories with aCAS latency of three and burst length of four in an embodiment of amethod for active termination control, in accordance with the teachingsof the present invention.

FIG. 12 shows a timing diagram for a read operation in memories with aCAS latency of three and burst length of four in an embodiment of amethod for active termination control including extending activetermination control, in accordance with the teachings of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description of the preferred embodiments,reference is made to the accompanying drawings which form a part hereof,and in which is shown by way of illustration, specific embodiments inwhich the inventions may be practiced. These embodiments are describedin sufficient detail to enable those skilled in the art to practice theinvention, and it is to be understood that other embodiments may beutilized and that process, electrical, or mechanical changes may be madewithout departing from the scope of the present invention. The followingdetailed description is, therefore, not to be taken in a limiting sense,and the scope of the present invention is defined only by the appendedclaims and their equivalents.

System

FIG. 1 shows an embodiment of a information handling system 100including a computer system 110 having a controller 120 coupled tomemory modules 130, 140, in accordance with the teachings of the presentinvention. Controller 120 is coupled to memory modules 130, 140 by,among other paths, a command bus 150. Memory modules 130, 140 includeone or more memory devices with active termination designed within eachmemory device. Further, information handling system 100 can also includea keyboard 160, a mouse 170, and a monitor 180 coupled to computersystem 110 to receive inputs from and display information to systemusers.

FIG. 2 shows an embodiment of a system 200 having a controller 220coupled to memory modules 230, 250, in accordance with the teachings ofthe present invention. In the embodiment of FIG. 2, memory module 230includes a module register 232 and memory devices 234-241, where moduleregister 232 is coupled to each of the memories 234-241 via a pluralityof lines 245. Similarly, memory module 250 includes a module register252 and memory devices 254-261. Module register 252 is coupled to eachof the memories 254-261 via a plurality of lines 265. Further, moduleregister 232 on memory module 230 and module register 252 on memory 250are coupled to a common command bus that is a system command bus 260 forsystem 200 to which controller 220 is also coupled. In addition tosystem command bus 260, controller 220 is coupled to module register 232via a chip select (CS#0) line 262 and a CS#1 line 264, and is coupled tomodule register 252 via a CS#2 line 266 and a CS#3 line 268. As can beappreciated that those skilled in the art, system 200 includes otherelements, other buses, and communication paths among the elements, whichare not shown. The figures focus on those elements for understanding thevarious embodiments according to the teachings of the present invention.

Module register 232 operates like a buffer on the module that re-drivesthe control signals from system control bus 260 to the eight memorydevices 234-241 on module 230. The address and controls are routed intomodule register 232, and then are re-clocked to memory devices 234-241on the next clock cycle. As a result, heavier loads can be placed on thesystem bus 260 without making the address and control lines too heavilyloaded. Other embodiments include 16, 32, or 36 memory devices on asingle memory module. The number of memory devices varies usually tohigher density memory modules. Module register 232 is coupled to thememory devices 234-241 via control lines 245 that are coupled to eachmemory device providing such signals as row address strobe (RAS), CAS,and write enable (WE). Other signals such as CS and clock enable (CKE)have separate lines from the register module 232. Memory devices 234-241primarily monitor their chip selects inputs to determine if a read or awrite is occurring for the given memory device. Further, each memorydevice 234-241 is provided with an active termination, rather thanhaving termination on the mother board.

Module register 232 is coupled to controller 220 by CS#0 line 262 andCS#1 line 264. Module register 252 is configured like module register232, but coupled to controller by CS#2 line 266 and CS#3 line 268. Thisconfiguration is used to access two groups of memory devices atdifferent times, with one group typically on one side of the memorymodule 230 and the other group on the other side of memory module 230.Such a configuration is said to be of rank two. However there aremodules that are double sided that only have one chip select, and henceare of rank one. The rank of the module determines how while reading orwriting to the memory devices, the signals are terminated. For a rank ofone, in some embodiments a memory device terminates itself. For a twomodule system, if the write or read operation is to module one, thenmodule two is the module that actually terminates. As a result, bothmodule register 232 of memory module 230 and module register 252 ofmemory module 250 monitors the system control bus 260 for read and writecommands, so that each memory module 230, 250 is provided withinformation regarding the read/write activities of each other tofacilitate correct termination.

Module Register

FIG. 3 shows an embodiment of a module register 300 having a decodingcircuit 302, a plurality of input command ports 304,306, 308, 310, 312,chip select ports 314, 316, and an active termination port 320 foroutputting an active termination control (ATC) signal, in accordancewith the teachings of the present invention. Clock signal (CLK) andinverted clock signal (CLK#) are received at ports 304, 306,respectively. Inverted row address strobe (RAS#), inverted columnaddress strobe (CAS#), and inverted write enable (WE#) signals arereceived at ports 308, 310, and 312, respectively, while CS0# and CS1#signals are received at ports 314, and 316, respectively. Moduleregister 300 re-clocks these signals and drives out CLK, CLK#, RAS#,CAS#, WE#, CS0#, and CS1# signals from ports 322, 324, 326, 328, 330,332, and 334, respectively, to memory devices to which it is coupled. Inaddition to re-clocking and driving control signals to memory devices,module register 300 provides a means for controlling active terminationof the memory device to which it is coupled.

Decoding circuit 302 uses the control signals received from a systemcommand bus to monitor whether a read or write command has been receivedby any memory module coupled to the same system command bus. Upondetecting a write or read command, decoding circuit 302 provides an ATCsignal at port 320. If a write command is decoded, the ATC signal isprovided from port 320 coincident with a write command being issued on amemory module. If a read command is decoded, the ATC signal is providedfrom port 320 one cycle after a read command issues on a memory module.Module register 300 monitors the system bus and then issues the activetermination control to the memory devices. As a result, there are notadditional pins on the module or on the chip set. Using module register300 with one port, or pin, on each memory device eliminates the need forATC ports on each memory module and ATC ports on a controller coupled toeach memory module. Module register 300 watches the system command busand controls the signals to the memory devices to which it is coupled,providing control of the ATC signal.

FIG. 4 shows an embodiment of a decoding circuit 400 of a moduleregister having an active termination port 402 for outputting an activetermination control signal based on signals received on chip selectports 404, 406 and a plurality of input command ports 408, 410, 412,414, and 416, in accordance with the teachings of the present invention.CLK and CLK # received at ports 416 and 414, along with WE#, CAS#, andRAS# received at ports 408, 410, and 412, respectively, are inputsignals for decoding circuit 400, which decodes commands to memorydevices selected. CS1# or CS0# at ports 404, 406, respectively, are usedin logic circuits to enable an output ATC signal, or pulse. For a twomodule system, CS0# and CS1# enable the output of the ATC signal on onememory module, while on the other memory module memory devices areselected for read and write operations.

Decoding circuit 400 is a command decoding structure that includes a setof gates decoding either a read command or a write command. If a writecommand propagates through decoding circuit 400 of a module register, anATC signal would be transmitted from port 402 to memory devices coupledto the module register. A read command that propagates through decodingcircuit 400 of a module register to transmit an ATC signal from port 402must first propagate through latch 418. Latch 418 provides a one clockcycle delay relative to the issuance of a read command from anothermodule register.

Memory

FIG. 5 shows an embodiment of a memory 500 including a control logic 502coupled to an active termination control port 504 for receiving anactive termination control signal and coupled to an active termination505, in accordance with the teachings of the present invention. Controllogic 502 logic includes timing circuitry to turn on and to turn off theactive termination. Control logic 502 represents a standard memorycontrol logic along with additional circuitry or state machine forcontrolling the state of the active termination on the memory. Forconvenience, FIG. 5 does not contain all the elements of a memory, butcontains those elements of a memory necessary for understanding theembodiments discussed, as can be appreciated by those skilled in theart.

In addition to receiving an ATC signal at port 504, control logic 502receives CKE, CLK#, and CLK at ports 506, 508, 510, respectively. Memory500 also receives command signals CS#, WE#, CAS#, and RAS# at ports 512,514, 516, and 518, respectively, that are decoded in command decode 520.In addition, memory 500 has one or more mode registers 522 as part ofcontrol logic 502 or coupled to control logic 502. The one or more moderegisters 522 are programmed with information for operating memory 500including CAS latency, operating mode, burst length, and burst type.Additional operating information can be contained in the one or moremode registers 522, depending on the particular memory.

Memory 500 also includes an address bus 524, a data bus 526, and amemory circuit 528 that contains data stored in memory 500. Memorycircuit 528 is coupled to address bus 524 for receiving informationidentifying the location for reading or writing data from data bus 526.The identification of the location is contained in BA0-BA1 for selectinga memory bank and in A0-AX for selecting an address within a memorybank. The management of the read and write operations is performed bycontrol logic 502 upon receiving commands from a processor such ascontroller 220 of FIG. 2. The read and write operations of memory 500are controlled using a delay lock loop having a CLK input to adjusttiming provided to drivers 532. The read and write operations arefurther controlled with a data strobe DQS that is provided by a DQSgenerator 534 suppling drivers 532 to control the DQS placed on DQS line536. In addition, the drivers also clock out data 324 received frommemory circuit 314 for transferral to data bus 526 in data bus locationsDQ0-DQX.

Memory 500 uses one or more registers as mode registers in whichoperating information is programmed into memory 500 by a controller,typically, on initialization or boot up (start of system). As mentioned,this information includes CAS latency, operating mode, burst length,burst type. As is known, the burst length determines the maximum numberof column locations that can be accessed for a given read or writecommand. Typically, the burst type is either sequential or interleaved,and the CAS latency is the number of clock cycles between theregistration of a read command by memory 500 and the availability of thefirst bit of output data from memory 500. The operating mode can eitherbe normal operation or normal operation with a reset of the delay lockloop (DLL). The one or more mode registers 522 can also be programmedwith information for controlling active termination.

Control logic 502 includes a timing circuit to turn on the activetermination at a predetermined time after an active termination controlsignal is received at the active termination control port. The turn-onof the active termination is set by memory 500 using one or more bitsdefining a CAS latency. The turn-on of the active termination canfurther be adjusted by an additive latency (AL) that is also programmedinto one or more mode registers. In an embodiment, the timing circuitryof control logic 502 is configured to turn-on active termination at theCAS latency minus two clock cycles plus the additive latency. In oneembodiment, the additive latency is zero. The control logic alsoincludes a timing circuit to turn off the active termination at apredetermined time after turning the active termination device on. Inone embodiment, control logic 502 is configured to use the bits definingthe burst length to set a turn off time for the active termination. Forconvenience, the number of cycles equal to the BL will also be referredto as burst length, BL. The timing circuit of control logic 502 sets aturn off time for active termination at a burst length divided by two,plus one and one-half a clock cycle after turning on the one activetermination. A burst length for a DDR is divided by two, since one databit is read out on a rising edge of a clock and another data bit is readout on a falling edge of the same clock. For a memory with one data bitread for one clock cycle, the turn off time for the active terminationwould be the burst length plus one and one-half a clock cycle afterturning on the one active termination.

In one embodiment, memory device 500 has active termination withmultiple termination values. The one or more mode registers contain oneor more bits to select one of the multiple active termination values. Inan embodiment, the multiple active termination values are 75 ohms and150 ohms. In one embodiment, the 75 ohm termination value is used whenthe memory is in a two module system, the 150 ohm termination value isused when the memory is in a one module system.

In a two module or two slot system, command signals to write or read tomemory devices on one module is accompanied by ATC turn on signals tomemory devices on the other module. However, in systems with only onemodule, there is no second module for active termination. In a onemodule system, each memory self terminates for write operations and doesnot do anything for read operations. To accomplish this self terminationfor writes in a one module system, memory 500 includes one or more bitsin one or more mode registers 522 that indicates that memory 500 is in asingle slot or a dual slot system. Memory 500 has logic circuitry suchthat whenever one or more bits selects a single slot system, memory 500is enabled to ignore a received active termination control signal. Whenmemory 500 is programmed on initialization as a single slot system, theprogrammed bits are used to turn on self termination upon receiving awrite command using the CAS latency and additive latency information inthe one or more mode registers 522. The active termination is turned offafter turning on the active termination using burst length informationprogrammed in the one or more mode registers 522.

In another embodiment, memory 500 includes one or more mode registerswith information that enables or disables active termination.

Thus, one or more mode registers are used to turn-on and turn-off activetermination on memory 500 based on the information programmed into theseregisters. This configuration provides more programmable control thanusing a external signal to turn on active termination and anotherexternal signal to turn off active termination, or equivalently, turningactive termination on and off with the two transitions of a singleactive termination signal.

Memory 500, as well as module register 300 and controller 220, can eachbe realized as a single integrated circuit. Memory 500 can be formed ona semiconductor die using a substrate, where the substrate is a materialsuch as silicon, germanium, silicon on sapphire, gallium arsenide, orother commonly used semiconductor material. The elements of memory 500are fabricated using conventional processing means for forming thevarious circuits within the semiconductor material and for providingelectrical connections for coupling to an address bus, a data bus, andcontrol lines for communication with a controller or a processor.

The various embodiments of memory 500 along with the various embodimentsof module register 300 of FIG. 3 can be coupled with a controller suchas controller 220 of FIG. 2 to form system 200 to provide a system withthe ability to manage its active termination control. Further, system200 can use one or more controllers having various embodiments ofcontroller 220 to program the one or more mode registers 522 of eachmemory 500 to which it is coupled independent of the other memories.

Data Structure

FIG. 6 shows an embodiment of an extended mode register having bitlocations, which provide information for active termination control, inaccordance with the teachings of the present invention. The extendedmode register includes bit locations 0, 1, 2 for information regardingdelay lock loop(DLL), drive strength (DS), and flow control (QFC),respectively. Location E0 provides for DLL enable/disable. Location E1provides for information on drive strength, and E2 provides for QFCdisabling of flow control. The extended mode register of a memory suchas memory 500 of FIG. 5 is operatively coupled to the address bus 524for programming by a controller such as controller 220 of FIG. 2.Controller 220, or an intermediate controller, programs information intothe extended mode register during initialization using the address bus.Generally, the BA1, BA2 locations of the address bus are used todistinguish between programming a standard mode register of memory 500and an extended mode register. Typically, BA1=0 and BA0=0 is used toprogram a standard mode register, while BA1=0 and BA1=1 is used toprogram a standard mode register.

The extended mode register can be used to program one or mor bits foruse in active termination control, since the bits, 3-11, for operatingmode have not been completely set by a standardization body. In oneembodiment, the data structure for the extended mode register includes afield containing data representing a single slot or a dual slot memorysystem. The field includes at least one bit for selecting a single slotor a dual slot system. In another embodiment, the data structure for theextended mode register includes a field containing data representingmultiple termination values for a memory device. The field includes oneor more bits for selecting either a 75 ohm termination value or a 150ohm termination value. In another embodiment, the data structure for theextended mode includes a field having one or more bits containing datarepresenting enabling or disabling active termination control for amemory.

Alternatively, the active termination information is programmed into oneor more mode registers other than the standard mode register and theextended mode register, both of which usually adhere to a data structuredefined by a standardization body such as JEDEC. CAS latency and burstlength are typically programmed into the standard mode register.

FIG. 7 shows an embodiment of a mode register using bit locations, whichprovide information for active termination control, in accordance withthe teachings of the present invention. Bit locations 12, 13 areoperatively coupled to address locations BA0, BA1, respectively toprovide identification of the mode register to be programmed oninitialization. The remaining bit locations, 0-11, are operativelycoupled to address bus locations A0-A11, respectively. The bitlocations, 0-11, can be used for active termination control. In oneembodiment, the data structure for the mode register includes a fieldcontaining data representing a single slot or a dual slot memory system.The field includes at least one bit for selecting a single slot or adual slot system. In another embodiment, the data structure for the moderegister includes a field containing data representing multipletermination values for a memory device. The field includes one or morebits for selecting either a 75 ohm termination value or a 150 ohmtermination value. In another embodiment, the data structure for themode includes a field having one or more bits containing datarepresenting enabling or disabling active termination control for amemory.

As mentioned previously, the mode registers of a memory are programmedby a controller during initialization of the memory. Alternately, themode registers can be programmed after initialization using a specifiedcommand sequence. Further, the mode registers of FIG. 6 and FIG. 7 areprogrammed by a controller providing a data signal for the memoryembodied in a set of electrical signals including data representing asingle slot or a dual slot system that includes a data portion forselecting the single slot or the dual slot system. The data signalincludes a data portion for selecting a single slot or a dual slotsystem with at least one bit for selecting a single slot or a dual slotsystem. With the data portion configured to select a single slot system,the data portion programs the memory to ignore a received activetermination control signal. In another embodiment, the data signalfurther includes data representing selection of multiple activetermination values with a data portion having one or more bits to selecteither a 75 ohm termination value or a 150 ohm termination value. Inanother embodiment, the data signal further includes data representingenabling or disabling an active termination control in the memory devicewith a data portion having one or more bits to enable or disable theactive termination control.

The one or more mode registers are programmed in a memory oninitialization of the memory by a controller or processor on boot up, orstart up. The mode registers are programmed with data including dataportions as discussed above. The controller programs these moderegisters based on instructions stored in a computer readable mediumthat the controller accesses for initialization instructions. Thiscomputer readable medium may be memory locations within the controlleror any other computer readable medium operatively coupled to thecontroller. The computer-readable medium has computer-executableinstructions for performing a method including determining a set of bitsto be sent to and loaded into one or more registers of a memory,arranging the bits in a predetermined format, and outputting the set ofbits. In one embodiment, the set of bits includes at least one bit forselecting a single slot or a dual slot system. When the set of bitsindicates the selection of a single slot system, the outputting of theset of bits to a memory programs the memory to ignore a received activetermination control signal. Additionally, the computer-readable mediumcan include in the set of bits one or more bits, for selecting multipletermination values. For instance, the one or more bits are provided forselecting a 75 ohm termination value or a 150 ohm termination value. Inanother embodiment, the set of bits additionally includes one or morebits for enabling or disabling active termination control. It can beappreciated by those skilled in the art, that the computer readablemedium accessed by a controller or processor can be of any computerreadable form such as, but not limited to, CD-ROMs, nonvolatile ROM,ROM, and RAM.

Operation

FIG. 8 shows a flow diagram of an embodiment for a method for activetermination control, in accordance with the teachings of the presentinvention. A module register such as module register 300 of FIG. 3 isused in system 200 of FIG. 2 as module registers 232 and 252. At block802, module register 232 monitors system command bus 260. At block 804,a determination is made as to whether the command is a predeterminedcommand. At block 806, in response to determining that a predeterminedcommand is on command bus 260, an active termination control signal isissued.

In one embodiment, module register 232 monitors the command bus for awrite command or a read command, while also monitoring the chip selector inverted chip select signals that it receives from controller 220. Ina two slot, or two module, system, module register 232 uses the chipselect information to determine whether or not to output an ATC signal.For instance, if the write or read command is for memory on module one,the active termination is performed on module two. Thus, in FIG. 2, witha write or read to memory module 230, module register 252 provides anATC signal for active termination on memory devices on module 250. If awrite command for memory devices on memory module 230 is detected,module register 252 generates an ATC signal coinciding with the moduleregister 232 issuing a write command. Both the ATC signal and the moduleregister generated write command are issued a clock cycle after thewrite command is monitored from the system command bus 260. If a readcommand for memory devices on memory module 230 is detected, moduleregister 252 generates an ATC signal one clock cycle after the moduleregister 232 issues a write command. The module register generated readcommand is issued a clock cycle after the read command is monitored fromthe system command bus 260, with the ATC signal generated two clockcycles after the read command is monitored from the system command bus260.

FIG. 9 shows a flow diagram of another embodiment for a method foractive termination control, in accordance with the teachings of thepresent invention. At block 902, an active termination control signal isreceived. At block 904, active termination is turned on. A memory suchas memory 500 of FIG. 5 is used on memory modules 230, 250 in system 200of FIG. 2. Memory 500 receives an ATC signal, and turns on activetermination based on information in one or more mode registers 522.Turning on active termination occurs at a predetermined time afterreceiving the active termination control signal. In one embodiment, theactive termination is turned on based on information regarding CASlatency and additive latency programmed in one or more mode registers.The turn on time is set at about a CAS latency less two clock cyclesplus an additive latency after receiving the ATC signal. For example,for a CAS latency of four programmed in a standard mode register and anadditive latency of zero, the active termination turns on two clockcycles after the ATC signal is received. In another embodiment, for amemory without additive latency, active termination is set at about aCAS latency less two clock cycles after receiving the ATC signal. It canbe appreciated by those skilled in the art, that the predetermined timefor turning on the active termination can be set using other parameters.Other predetermined turn on times include using the CAS latency minus anadditional number of clock cycles, where the additional number of clockcycles can be any number of clock cycles, including fractional clockcycles, less than the CAS latency. It is a matter of selecting theadditional clock cycles such that the active termination is turned onfor a short period before the data is read or written.

The active termination is maintained in an on state for a predeterminedlength of time. The predetermined time is determined using informationprogrammed in one or more mode registers. In one embodiment, thepredetermined time is set at about a burst length divided by two plusone and a half clock cycles. For a DDR, the burst length is divided bytwo. For a memory with one bit read or written in one clock cycle, theburst length is not divided by two. For instance, for a burst length ofeight programmed in a standard mode register, the active termination ismaintained on for five and one-half clock cycles after the activetermination is turned. It can be appreciated by those skilled in theart, that the predetermined length of time for maintaining the activetermination can be set using other parameters. Other predeterminedlengths of time include using the burst length or burst length dividedby two plus an additional number of clock cycles, where the number ofclock cycles can be 1, 1.5, 2, 2.5, or other number. It is a matter ofselecting the additional clock cycles such that the active terminationis still on for a short period after the data is read or written.

In an embodiment, a method for active termination control in a memoryincludes accessing information indicating an enable or disable of anactive termination control, determining a turn on time for the activetermination, and determining a turn off time for the active termination.The information indicating an enable or disable of the activetermination control is provided by at least one bit in a mode register.The one or more bits indicating an enable or disable of the activetermination control is combined with latency information to set a turnon time at a predetermined period after receiving an ATC signal. In oneembodiment, the predetermined time is set to a CAS latency less twoclock cycles plus an additive latency after receiving an ATC signal.Alternately, there is no additive latency or the additive latency is setto zero. The turn off time is determined by combining the informationindicating an enable or disable of an active termination control withburst length information. In one embodiment, determining a turn off timefor the active termination control includes setting the turn off time toa burst length divided by two plus a multiple of a clock cycle after theturn on time of the active termination. A convenient multiple of a clockcycle is one equal to about one and one-half clock periods.

A memory such as memory 500 of FIG. 500 uses the received ATC signal,the CAS latency and burst length programmed into the mode register toset the turn on and turn off times for active termination. Thisoperation is appropriate for a two slot system, where memory devices towhich data is written or from which data is read are on a memory modulein one slot, and the memory devices for active termination are on amemory module in the other slot. For a one slot system, another methodcan be applied. In one embodiment, a method for active terminationcontrol in a memory includes receiving an active termination controlsignal, ignoring the received active termination control signal, andturning on active termination in response to receiving a write command.The information for ignoring the received active termination controlsignal is programmed in a mode register of the memory. This informationis typically stored as one or more bits in a mode register of thememory.

As with a two slot system, the turn on and turn off times are set usinglatency information and burst length information, respectively. Turningon active termination occurs at a CAS latency less two clock cycles plusan additive latency after receiving the write command. In oneembodiment, setting the turning on time for he active terminationincludes using a zero additive latency. The active termination ismaintained for a predetermined time after receiving write command. Inone embodiment, the predetermined time is about a burst length dividedby two plus one and a half clock cycles. In a one slot system, notermination is required for read operations.

FIG. 10 shows a flow diagram of another embodiment for a method forextending active termination control, in accordance with the teachingsof the present invention. A memory such as memory 500 of FIG. 5 is usedon memory modules 230, 250 in system 200 of FIG. 2. At block 1002,memory 500 receives an active termination control signal. At block 1004,memory 500 sets turn on time for active termination. At block 1006,memory 500 sets turn off time for active termination. At block 1008,memory 500 determines whether another active termination control signalhas arrived. If another active termination control signal has arrived,memory 500 returns to block 1006 to set a new turn off based on thelatest active termination control signal. At block 1010, if anotheractive termination control signal has not arrived, memory 500 turns offthe active termination at the last set turn off time, which is based onthe last ATC signal received. Thus, memory 500, in response to receivinganother ATC signal while the active termination is on, maintains theactive termination on for a predetermined time set relative to the lastATC signal received. Memory 500 uses the same procedure and parametersto determine the turn-off time based on the last ATC signal received asit performed for setting a turn-off time for the first ATC signalreceived. For instance, on receiving a second and last ATC signal, atimer is reset for the active termination to last a burst length dividedby two plus one and one-half clock cycles after a turn on timeassociated with the last active termination control signal.

FIG. 11 shows a timing diagram 1100 for a write operation to memorieswith a CAS latency of three and burst length of four in an embodiment ofa method for active termination control, in accordance with theteachings of the present invention. Timing diagram 1100 can be appliedto system 200 of FIG. 2 for discussion purposes. At 1102, a writecommand on a system command bus 260 is detected by module registers 232,252. Since this command is detected by module register 232, 252effectively snooping the system command bus 260, it is indicated in FIG.11 as a command edge connect. At 1102, WR RO means write to rank zeroindicating a write command for writing to memories of the first rank onmodule one. The term, WR R2, meads a write to rank two indicating awrite command to memories on the second module. Thus, on the commandbus, controller 220 is sending write commands to memory module 230 inslot 0 and memory module 250 in slot 1 with two different writes. At1104, module register 232, since it's clocked, delays the write commandon memory module 230 by one clock cycle as it goes through the moduleregister. At 1106, module register 252 fires an ATC signal for memorymodule 250 in slot 1 coincident with the write command from memoryregister 232 to slot zero, while module register 232 does not send outan ATC pulse or signal to memory module 230.

At 1108, the active termination turns on for memory module 250 in slot 1at a CAS latency minus two clock cycles. For the CAS latency set atthree, the active termination turns on one clock cycle after the memorydevices on memory module 250 in slot 1 receive the ATC signal. At 1110,on the DQ lines, the data in for rank 0, module 230, begins at CASlatency minus one with a burst length of four, driven by DQS.

At 1112, a write to rank two indicating a write command to memories onthe second module is generated by controller 220 on system command bus260. At 1114, module register 252 of memory module 250 regenerates thewrite command for memory devices on memory module 250 in slot 1.

At 1116, module register 232 of memory module 230 generates an ATC pulseor signal for memory devices on memory module 230 in slot 0. At 1118,since the CAS latency is three, the active termination for memory module230 in slot 0 turns on one clock cycle after receiving the ATC signalthat coincides with the write command regenerated by memory register 252for memory devices on memory module 250 in slot 1. At 1120, on the DQlines, the data in for rank 2, module 250, begins at CAS latency minusone with a burst length of four, driven by DQS.

The active termination on memory module 250 in slot 1 turns off at theburst length of 4 divided by 2, plus one and one-half clock cyclesproviding an off time of about three and one-half clock cycles afterturning on. As can be seen from FIG. 11, the active termination onmemory module 250 in slot 1 completely brackets the writing of data inmemory devices on memory module 230 in slot 0. Likewise, the activetermination on memory module 230 in slot 0 completely brackets thewriting of data in memory devices on memory module 250 in slot 1. Forthe case demonstrated in FIG. 11, there is a period of time for whichthe active termination on memory module 230 in slot 2 and the activetermination on memory module 250 in slot 1 are both on. This does notcause any problems since there is nothing on the data bus at that time.The effective active termination for system 200 is shown at 1122, whichdemonstrates that active termination is effectively maintained for thetwo write commands sequence close together in time.

Since the turning on and off of the active termination occurs on memorydevices on different memory modules that use a common DQ bus, the memorydevices on both memory modules need to operate with the same CASlatency, and the same burst length. In addition, the command bus needsto be shared by both memory modules, since the generation of an ATCsignal on one memory module and subsequent turning on and off of theactive termination is performed assuming command operations are beingperformed on the other memory in an associated time frame.

FIG. 12 shows a timing diagram 1200 for a read operation in memorieswith a CAS latency of three and burst length of four in an embodiment ofa method for active termination control including extending activetermination control, in accordance with the teachings of the presentinvention. Timing diagram 1200 can be applied to system 200 of FIG. 2for discussion purposes. At 1202, a read command on a system command bus260 is detected by module registers 232, 252. RD RO means read to rankzero indicating a read command for reading memories of the first rank onmodule one. The term, RD R2, meads a read of rank two indicating a readcommand to memories on the second module. At 1204, module register 232,since it's clocked, delays the read command on memory module 230 by oneclock cycle as it goes through the register. At 1206, module register252 on the memory module 250 fires an ATC signal that is delayed oneclock cycle from module register 232 issuing a read command for memorieson memory module 230. This coordination in timing is facilitated bymodule registers 232, 252 both receiving common clock signals and bothsnooping a common system bus. Module register 232 does not send out anATC pulse or signal to memory module 230 to which a read operation is tobe performed on memory module 230 in slot 0.

At 1208, the active termination turns on for memory module 250 in slot 1at a CAS latency minus two clock cycles. For the CAS latency set atthree, the active termination turns on one clock cycle after the memorydevices on memory module 250 receive the ATC signal. The memories alsodetermine a turn off time at the burst length divided by two plus oneand one half clock cycles after turning on the active termination. For aburst length of four, the memories set a turn-off time at three andone-half clock cycles after the turning on of the active termination. At1210, on the DQ lines, the data out for rank 0, module 230, begins atCAS latency minus one with a burst length of four, driven by DQS.

However, prior to turning on the active termination for memory deviceson memory module 250 in slot 1, controller 220 issues another readcommand at 1212. At 1214, module register 232 of memory module 230 inslot 0 issues a read command to the memory devices on memory module 230one clock cycle after detecting the 1212 read command on the systemcommand bus 260. One clock cycle after module register 232 issues the1214 read command, at 1216, module register 252 on memory module 250generates another ATC signal for the memories on memory module 250 inslot 1. The memories receiving this second ATC signal on memory module250 determine a new active termination turn on time and a new turn offtime based on the arrival of the second ATC signal. From FIG. 12, thenew turn on time begins at two clock cycles after the first turn on timeat 1218, which is before the scheduled turn off time determined from thefirst ATC signal received. The memories will reset the on time for theactive termination based on the second ATC signal received and will setthe turn off time at three and one-half clock cycles for the newlydetermined turned on time. Thus, the active termination stays on betweenthe two read operations for memories on memory module 230 in slot 0.

At 1220, on the DQ lines, the data out for rank 0, module 230, is readout in response to the second read command to the memories of memorymodule 230 in slot 0. This data is immediately read out following thedata read with respect to the first read command. As can be seen in FIG.12, the complete read out of data from memory module 230 in slot 0following the two read commands is completely bracketed with the activetermination in an on state in memory devices on memory module 250 inslot 1.

At 1222, prior to the completion of the read operations for memories onmemory module 230 in slot 230, controller 220 issues a read command formemories on memory module 250 in slot 1. At 1224, module register 252issues a read command to memory devices on memory module 250 one clockcycle after detecting a read command on the system command bus 260. Oneclock cycle after memory register 252 issues a read command, memorymodule 232 generates an ATC signal for memory devices on memory module230 in slot 0. Then one cycle later, which is the CAS latency minus twoclock cycles, the active termination is on, at 1228, in memory deviceson memory module 230 in slot 0. At 1230, on the DQ lines, the data outfor rank 2, module 250, begins at CAS latency minus one with a burstlength of four, driven by DQS. At 1232, the effective active terminationfor the system brackets both reads on memory module 230 and the read onmemory module 250. The on state of active termination on memory deviceson memory module 230 overlaps the on state of active termination onmemory devices on memory module 250 for a short period of time. Duringthis overlap period of time, no data is on the system data bus.

For all the read and write commands, the turn on times and turn offtimes are the same. For a CAS latency of three and burst length of 4,the turn on time is one clock cycle after receiving the ATC signal,while the turn off time is three and one-half clock cycles after turningon the active termination. The turn off time is modified if additionalread or write commands are monitored causing new active termination turnon times to be determined that are scheduled prior to turning off theactive termination from a previous read or write command. Of course, therelative turn on and turn off times can be changed by reprogramming allthe memories with a CAS latency different than three and a burst lengthdifferent than four. However, as noted earlier, since read and writeoperations are being performed on memories devices on one memory moduleand active termination is being performed on memories devices on othermemory, the timing requirements for all memories are the same with allmemories having the same CAS latency and burst length along withreceiving a common clock and being coupled to a common bus.

CONCLUSION

The above structures and methods have been described by way of example,and not by way of limitation, with respect to active termination throughan on module register. A method and apparatus are provided for activetermination control in a memory by an module register providing anactive termination control signal to the memory. The module registermonitors a system command bus for read and write commands. In responseto detecting a read or write command, the module register generates anactive termination control signal to the memory. The memory turns onactive termination based on information programmed into one or more moderegisters of the memory. In one embodiment, the CAS latency is used todetermine a turn on time, and the burst length is used to determine aturn off time following the turn on of the active termination.

As a result of this method, the number of ports, or pins, to providetermination in a system is reduced. In the various embodiments, pins foractive termination control are not need on a system controller, amotherboard, or memory modules.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. It is to be understood that the above description is intendedto be illustrative, and not restrictive. Combinations of the aboveembodiments, and other embodiments will be apparent to those of skill inthe art upon reviewing the above description. The scope of the inventionincludes any other applications in which the above structures andfabrication methods are used. The scope of the invention should bedetermined with reference to the appended claims, along with the fullscope of equivalents to which such claims are entitled.

1. A module register comprising: a decoding circuit; and an activetermination control port coupled to the decoding circuit to output anactive termination control signal.
 2. The module register of claim 1,wherein the module register includes: a plurality of input command portscoupled to the decoding circuit, the plurality of input command ports tomonitor a system command bus; and one or more chip select ports coupledto the decoding circuit.
 3. The module register of claim 1, wherein thedecoding circuit includes a logic circuit to decode a write command anda read command.
 4. The module register of claim 3, wherein the decodingcircuit includes a logic circuit to delay the output of the activetermination control signal a clock cycle after an expected time to issuea read command, if a read command from a system command bus is decoded.5. The module register of claim 4, wherein the expected time to issue aread command is about a clock cycle after the read command from thesystem command bus is issued.
 6. The module register of claim 3, whereinthe decoding circuit includes a logic circuit to issue the activetermination control signal coinciding with an expected time to issue awrite command, if a write command from a system command bus is decoded.7. The module register of claim 6, wherein the expected time to issue awrite command is about a clock cycle after the write command from thesystem command bus is issued.
 8. The module register of claim 6, whereinthe module register is configured as an integrated chip having aconnection to couple to one or more memories.
 9. An integrated circuitcomprising: a plurality of input command ports; one or more clock portsto receive clock signals; a decoding circuit coupled to the plurality ofinput command ports and the one or more clock ports; and an activetermination control port coupled to the decoding circuit to output anactive termination control signal.
 10. The integrated circuit of claim9, wherein the decoding circuit includes a logic circuit to decode awrite command and a read command.
 11. The integrated circuit of claim10, wherein the decoding circuit includes logic circuits to delay theoutput of an active termination control signal associated with a readcommand for a clock cycle longer than outputting an active terminationcontrol signal associated with a write command.
 12. A memory modulecomprising: one or more memory devices; and a module register coupled tothe one or more memory devices, the module register including: adecoding circuit; and an active termination control port coupled to thedecoding circuit to output an active termination control signal.
 13. Thememory module of claim 12, wherein the memory register includes: aplurality of input command ports coupled to the decoding circuit, theplurality of input command ports to monitor a system command bus; andone or more chip select ports coupled to the decoding circuit.
 14. Thememory module of claim 12, wherein the decoding circuit includes a logiccircuit to decode a write command and a read command.
 15. The memorymodule of claim 14, wherein the decoding circuit includes a logiccircuit to delay the output of the active termination control signal aclock cycle after an expected time to issue a read command, if a readcommand from a system command bus is decoded.
 16. The memory module ofclaim 14, wherein the decoding circuit includes a logic circuit to issuethe active termination control signal to coincide with an expected timeto issue a write command, if a write command from a system command busis decoded.
 17. The memory module of claim 12, wherein the one or morememory devices includes a double data random access memory.
 18. A systemcomprising: a controller; one or more memory modules coupled to thecontroller, each memory module including a module register and one ormore memory devices, each memory device coupled to the module register,the module register including: a decoding circuit; and an activetermination control port coupled to the decoding circuit to output anactive termination control signal.
 19. The system of claim 18, whereinthe module register includes: a plurality of input command ports coupledto the decoding circuit, the plurality of input command ports to monitora system command bus; and one or more chip select ports coupled to thedecoding circuit.
 20. The system of claim 18, wherein the decodingcircuit includes a logic circuit to decode a write command and a readcommand.
 21. The system of claim 20, wherein the decoding circuitincludes a logic circuit to delay the output of the active terminationcontrol signal a clock cycle after a read command is issued on a moduleif a read command from the system command bus is decoded.
 22. The systemof claim 20, wherein the decoding circuit includes a logic circuit toissue the active termination control signal to coincide with the issuingof a write command on a module if a write command from the systemcommand bus is decoded.
 23. The system of claim 18, wherein the one ormore memory devices includes a double data random access memory.
 24. Thesystem of claim 18, wherein the system includes a two module system. 25.The system of claim 18, wherein the system includes a one module system.26. The system of claim 18, wherein the system includes an informationhandling system.
 27. The system of claim 18, wherein the informationhandling system includes a computer system.